The drain-source on-resistance of a power MOS device determines its application power. When the on-resistance is small, the device provides an excellent switching characteristics with a relatively greater output current, resulting in a stronger drive capability. Thus, it is desirable to reduce the on-resistance of power MOS devices.
It can be seen that, according to the formula for calculating the on-resistance R=(ρ*L)/(d*W), the greater the channel width W, the lower the on-resistance R. Therefore, multiple LDMOS (Lateral Double-diffused MOS) basic units coupled in parallel may be used in a power MOS device to achieve an increase in total channel width to thereby reduce the on-resistance.
Existing power MOS devices that employ multiple basic units of LDMOS coupled in parallel include an internal chip device and an external chip device, with the internal chip device including multiple basic units of LDMOS coupled in parallel. The external chip device is located in the boding pad region external to the chip. The bonding pad is used to connect the internal chip device to the outside, and is typically provided in an area outside the chip. The material of the bonding pad may be an electrically conductive metal such as copper or aluminum, and the bonding pad takes up about 5˜20% of the area of the die. FIG. 1 is a schematic diagram of a conventional power MOS device having multiple basic units of LDMOS coupled in parallel. The striped region represent the multiple basic units of LDMOS and the blocked regions represent the bonding pad area. In existing designs, in consideration of the potential of damage to components below the bonding pad due to the stress from packaging and wiring, it is common to avoid having components below the bonding pad. FIG. 2 is a cross-sectional view of the power MOS device having multiple basic units of LDMOS coupled in parallel of FIG. 1. As shown, there are multiple basic units of LDMOS 100 and a bonding pad region 101, with a portion of the upper metal 103 that is not covered by the passivation layer region 102 as the bonding pad.
To further reduce the on-resistance, there is a need to increase the number of basic units of LDMOS. As there are no components disposed below the bonding pad, the area of the die occupied by the basic units of LDMOS tends to increase and the number of the basic units of LDMOS increases. This would result in higher cost.
Accordingly, the present disclosure provides a novel power MOS device structure that utilizes the area of the bonding pad region to effectively reduce the on-resistance without changing the size of chip area or cost.